1. Field of the Invention
The present invention relates to a memory controlling method and a memory controlling apparatus having communication capabilities required in transferring data between a memory including a DRAM (dynamic random access memory) divided into a plurality of blocks and a device having the capability of inputting and outputting data.
2. Description of the Related Art
According to a common technique, a DRAM is generally controlled in such a manner that read/write cycles and and refresh cycles are assigned to respective blocks of the memory so that when a read/write cycle is performed in a certain block, a refresh cycle is performed in another block, thereby ensuring that data can be transferred while maintaining the memory contents in the DRAM.
It is also known in the art to introduce competition between read/write and refresh cycles so that when a cycle is completed another cycle is started in accordance with predetermined priority, thereby ensuring that data transfer is performed without losing the contents of the DRAM.
However, in the former conventional technique, control signals are simultaneously applied to the respective blocks, and thus a large current is consumed when the control signals are simultaneously applied. That is, extremely great peaks appear in the current. Such large currents cause instantaneous variations in the power supply voltage, or result in noise. As a result, a reduction in the reliability of the apparatus occurs.
Although the latter conventional technique does not have such a problem, it has another problem that, in order to ensure that the contents of the memory are maintained without being lost, the ratio of the refresh cycles to the read/write cycles is often set to a value rather greater than required. This results in a reduction in the data transfer rate.